The present invention relates generally to data transfers for graphics processing units, and more particularly to preventing such data transfers from being interrupted.
An ingenious way to reduce costs for graphics processing systems has recently been developed by NVIDIA Corporation in Santa Clara, Calif. Specifically, the need for a local memory placed on a graphics card has been eliminated. These zero-frame-buffer graphics processors reduce costs and simplify manufacturing by eliminating multiple external memory devices and associated power supplies and board trace routing.
Instead of having a locally available memory, a zero-frame-buffer processor stores data in a system memory. That is, the zero-frame-buffer processor requests space in the system memory from the operating system, and uses this space to store display, computational, and other data. Details of this architecture can be found in co-pending and co-owned and co-pending U.S. patent application Ser. No. 11/253,438, titled Zero Frame Buffer, filed Oct. 18, 2006, by Yeoh et al., which is incorporated by reference. Another architecture includes a near-zero frame buffer, which is a smaller, limited memory used for special purposes, either on the graphics processor itself, or external to the device.
The elimination (or near elimination) of a local frame buffer provides many cost saving advantages. However, a zero-frame-buffer graphics processor does not have a local memory at its disposal; it relies on a system memory that is separated from the graphics processor by one or more devices, such as a Northbridge and CPU. As such, the ability of the graphics processor to read and write data from and to the system memory is dependent on the states and activities of these other devices. For example, if one of these other devices tie up the front-side bus for some amount of time, data transfers to and from the graphics processor may be interrupted and their completion delayed. One such interruption may occur when a CPU exits a low-power state during a transfer of data from a system memory to a graphics processor. When the CPU exits the low-power state, delays in data transfers from system memory are stalled. This can have particularly undesirable consequences when the data is display data, and the GPU runs out of data to display.
Thus, what is needed are circuits, methods, and apparatus that help to avoid these interruptions.